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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 january 1994 integrated circuits philips semiconductors TDA2579C synchronization circuit with synchronized vertical divider system for 60 hz
january 1994 2 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C features synchronization and horizontal part horizontal sync separator and noise inverter horizontal oscillator horizontal output stage horizontal phase detector (sync to oscillator) triple current source in the phase detector with automatic selection normal phase detector time constant is increased to fast during the vertical blanking period (external switching for vtr conditions not necessary) slow phase detector time constant and gated sync pulse operation are automatically switched on by an internal sync pulse noise level detection circuit fast phase detector time is switched on for locking time constant externally switchable inhibit of horizontal phase detector and video transmitter identification circuit during equalizing pulses and vertical sync pulse inhibit of horizontal phase detector during separated vertical sync pulse second phase detector for storage compensation of the line output stage 3-level sandcastle pulse generator automatic adaption of the burst key pulse width video transmitter identification circuit stabilizer and supply circuit for starting the horizontal oscillator and output stage directly from the mains rectifier horizontal output current with constant duty factor value of 55% duty factor of the horizontal output pulse is 55% when the horizontal flyback pulse is absent. vertical part f v = 60 hz (m) system vertical synchronization pulse separator without external components and two integration times zener diode reference voltage source for the vertical sawtooth generator and vertical comparator divider system with three different reset enable windows synchronization is set to 528 divider ratio when no vertical sync pulse and no video transmitter is identified divider window is forced to wide window when a vertical sync pulse is detected within the window provided by reset divider and end of vertical blanking period, on condition that the voltage on pin 18 is 1.2 v divider ratio is 528 (f v = 60 hz) for dc signal on pin 5 linear negative-going sawtooth generated via the divider system (no frequency adjustment) comparator with low dc level feedback signal output stage driver f v = 60 hz identification output combined with mute function start of vertical blanking is shifted to the start of the pre-equalizing pulses when the divider ratio is between 522 and 528 lines per picture guard circuit which generates the vertical blanking pulse level on the sandcastle output pin 17 when the feedback level at pin 2 is not within the specified limits. general description the TDA2579C is an integrated circuit generating all requirements for synchronization of its horizontal oscillator and output stage plus those of the vertical part which comprises a divider system, sawtooth generator, comparator and output stage. the TDA2579C is almost identical to the tda2579b. it is optimized for the m (60 hz) tv system. ordering information extended type number package pins pin position material code TDA2579C 18 dil plastic sot102
january 1994 3 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C quick reference data note 1. open collector loaded with external resistor to positive supply. symbol parameter conditions min. typ. max. unit supply i 16 minimum required current for starting horizontal oscillator and output stage 6.2 -- ma v 10 main supply voltage - 12 - v i 10 supply current - 70 - ma input signals v 5-9 sync pulse input amplitude 0.05 - 1v i 12 horizontal ?yback pulse input current 0.2 1 - ma v 2 vertical comparator input voltage ac (peak-to-peak value) - 0.8 - v dc - 1 - v output signals v 11 horizontal output voltage (open collector) i 11 = 25 ma -- 0.5 v v 1 vertical output stage driver (emitter follower) i 1 = 1.5 ma 5 -- v v 17 sandcastle output voltage levels burst key 9.8 -- v horizontal blanking - 4.5 - v vertical blanking - 2.5 - v v ideo transmitter identification output ; note 1 v 13 output voltage no sync pulse present -- 0.32 v i 13 output current no sync pulse present -- 5ma v 13 output voltage sync pulse present; divider ratio <576 - 7.6 - v
january 1994 4 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C mga791 1 nf 9 100 nf vertical/ horizontal sync separator noise inverter coincidence detector phase detector j 1 gating divider vertical zener reference vertical comparator sync pulse noise level detector j 1 reference vertical blanking vertical guard circuit vertical output noise detector antitop burst key sandcastle output horizontal oscillator j 2 reference flyback pulse protection pulse width modulator phase detector j 2 too low current protection horizontal output supply switch start circuit stabilizer video transmitter identification vertical/ oscillator sawtooth generator 12 10 16 15 8 5 13 18 7 6 11 4.7 nf w 6.8 k horizontal drive to pin 16 w 220 k TDA2579C flyback pulse input sandcastle output vertical drive vertical feedback 150 nf w 150 k to vertical deflection current measuring resistor 43 2 1 17 22 m f i 6.2 ma 68 nf 150 pf 6.8 m f w 1 k w 1.2 k video signal input 22 m f w 22 w 5.6 k 2.2 m f 47 nf w 15 k mute 60 hz 12 v w 33 k w 4.7 k 2.7 nf 12 v 14 r = s fig.1 block diagram.
january 1994 5 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C pinning symbol pin description v out 1 vertical driver output fb 2 vertical feedback input saw 3 vertical sawtooth generator vdc 4 vertical de?ection current output vid 5 video signal input csl 6 slicing level storage capacitor rsl 7 slicing level resistor j 1 8 phase detector j 1 gnd 9 ground (0 v) v p 10 main supply voltage (+12 v) h out 11 horizontal driver output flyb 12 horizontal ?yback pulse input mute 13 mute output h shift 14 horizontal picture shift capacitor h osc 15 horizontal oscillator frequency setting stab 16 start circuit stabilizer input sc 17 sandcastle output det 18 coincidence detector output fig.2 pin configuration. 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 mga790 v fb saw vdc vid csl rsl 1 gnd det sc stab h shift mute flyb h v p j TDA2579C osc out h out functional description the TDA2579C generates both horizontal and vertical drive signals, a 3-level sandcastle output pulse, a transmitter identification signal and 60 hz window information. the horizontal oscillator and horizontal output stage functions are started via the supply current into pin 16. the required current has a typical value of 5 ma which can be taken directly from the mains rectifier. the horizontal output transistor at pin 11 is not conducting until the supply current at pin 16 has reached its typical value. the starting circuit has a hysteresis of approximately 1 ma. the horizontal output current of pin 11 starts at a duty cycle of 60%. all other ic functions are enabled via the main supply voltage on pin 10. the pin 16 supply system enables slaved synchronized switch mode systems in which the horizontal output signal of the TDA2579C is used as master signal. in such a system the 12 v supply (main supply at pin 10) can be generated by the line output stage. an internal zener diode reference voltage is used for the vertical processing part. the ic embodies a synchronized divider system for generating the vertical sawtooth at pin 3. thus no vertical frequency adjustment is required. the circuit operation is restricted to the m (f v = 60 hz) system. vertical part (pins 1, 2, 3 and 4) the ic embodies a synchronized divider system for generating the vertical sawtooth at pin 3. the divider system has an internal frequency doubling circuit, thus the horizontal oscillator is operating at its nominal line frequency and one line period equals 2 clock pulses. no vertical frequency adjustment is required due to the divider system. the divider system operates with 3 different reset windows for maximum interference/disturbance protection. the windows are activated via an up/down counter. the counter increases its value by 1 each time the separated vertical sync pulse is within the window being searched. the count is reduced by 1 when the vertical sync pulse is not present. the reset of the counter system (clock pulse 0) is at half a line period after the start of the vertical pulse at pin 5.
january 1994 6 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C in accordance with the convention for the m system, field one line 1 number 1 starts at the first equalizing pulse, the reset of the divider system is at the start of line 4 for the first field and in the middle of line 265 for the second field. divider system m ode a: large ( search ) window divider ratio between 488 and 576. this mode is valid for the following five conditions: 1. divider is locking to a new transmitter. 2. divider ratio found, not being within the narrow window limits. 3. up/down counter value of the divider system operating in the narrow window mode decreases below count 1. 4. external forced setting. this can be achieved by loading pin 18 with a 220 w resistor to earth or by connecting a 3.6 v stabistor diode between pin 18 and ground. 5. a vertical sync pulse was detected within the interval provided by reset divider (at 528) and the end of the vertical blanking while the voltage at pin 18 is 1.2 v. m ode b: narrow window divider ratio between 522 and 528. the divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved vertical sync pulses in the large window mode. when count 12 is reached the vertical sync pulse is tested for the standard tv-norm being the divider ratio 525. when this value is valid for the 12th vertical pulse, the up/down counter is reset to 0 and the up/down counter tests for a valid 525 divider ratio. when at the 12th vertical pulse the divider ratio is not equal to n = 525 then the divider system remains in the narrow window mode and remains testing for the standard tv-norm. when the divider operates in this mode and a vertical sync pulse is missing within the window the divider is reset at the end of the window and the counter value is decreased by 1. at a counter value below count 1 the divider system switches over to the large window mode. m ode c: standard tv - norm divider ratio 525; f v = 60 hz. when the up/down counter has reached its maximum value of 12 in the narrow window mode and the divider ratio equals n = 525 the information applied to the up/down counter is changed such that now the standard divider ratio value is tested and the up/down counter is reset to 0. when the up/down counter reaches the value of 14 approved m tv-norm pulses the divider system is changed over to the standard divider ratio mode. in this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. a missed vertical sync pulse decreases the counter value by 1. when the counter reaches the value of 10 the divider system is switched over to the large window mode. the standard tv-norm condition provides maximum protection for video recorders playing tapes with anti-copy guards. m ode d: no tv transmitter found at pin 18 the voltage level is less than 1.2 v. in this condition, only noise is present and no vertical sync pulse is detected, the divider is reset to count 528. in this way a stable picture display at normal height is achieved. m ode e: video tape recorders in feature mode ntsc (m system) 3-speed video tape recorders it should be noted that some vtrs operating in the picture search mode, generate such distorted pictures that the no tv transmitter detection circuit can be activated as the voltage on pin 18 drops below 1.2 v. this would imply a rolling picture (mode d). in general vtrs do use a re-inserted vertical pulse in the feature mode. therefore the divider system has been designed such that the divider is forced to the wide window mode when v 18 is below 1.2 v and a vertical sync pulse is detected within the window provided by the reset divider at 528 and the end of the vertical blanking period. general the divider system also generates the anti-top-flutter pulse which inhibits the phase 1 detector during the vertical sync pulse. the width of this pulse depends on the divider mode. for the divider mode a the start is generated at the reset of the divider. in modes b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse sequence. the anti-top-flutter ends after the second equalizing pulse sequence. the vertical blanking pulse is also generated via the divider system. the start is at the reset of the divider while the blanking pulse ends at count 34, the middle of line 21 of field 1 and at the end of line 283 of field 2. the vertical blanking pulse generated at the sandcastle output pin 17 is made by adding the anti-top-flutter pulse and the blanking pulse. in this way the vertical blanking pulse starts at the beginning of the first equalizing pulse when the divider operates in the b or c mode.
january 1994 7 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C vertical sawtooth to generate a vertical linear sawtooth voltage a capacitor should be connected to pin 3. the recommended value is 150 nf to 330 nf. the capacitor is charged via an internal current source starting at the reset of the divider system. the voltage on the capacitor is monitored by a comparator which is also activated at reset. when the capacitor has reached a voltage value of 5.0 v the voltage is kept constant until the charging period ends. the charging period width is 26 clock pulses. at clock pulse 26 the comparator is switched off and the capacitor is discharged by an npn transistor current source the value of which can be set by an external resistor connected between pin 4 and ground (pin 9). pin 4 is connected to a pnp transistor current source which determines the current of the npn current source at pin 3. the pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a typical voltage of 7.5 v. the recommended operating current range is 10 to 75 m a. the resistor at pin 4 should be 100 to 770 k w . by using a double current mirror concept the vertical sawtooth pre-correction voltage can be set to the required value by external components connected between pins 3 and 4 or by superimposing a correction voltage in series with the earth connection of the resistor connected to pin 4. the vertical amplitude is set by the current of pin 4. vertical feedback the vertical feedback voltage of the output stage has to be applied to pin 2. for the normal amplitude adjustment the values are dc = 1 v and ac = 0.8 v (p-p). the low dc voltage value improves the picture bounce behaviour as less parabola compensation is required. even a dc-coupled feedback circuit is possible. vertical guard the ic also contains a vertical guard circuit. this circuit monitors the vertical feedback signal on pin 2. when the level on pin 2 is below 0.35 v or higher than 1.85 v the guard circuit inserts a continuous voltage level of 2.5 v in the sandcastle output signal of pin 17. this results in blanking of the picture displayed, thus preventing a burnt-in horizontal line. vertical driver output the driver output is at pin 1, it can deliver a drive current of 1.5 ma at 5 v output. the internal impedance is approximately 170 w . the output pin is also connected to an internal current source with a sink current of 0.25 ma. integration time of the vertical synchronization pulse separator the vertical sync separator has two integration times: long time; typical 19 m s, valid for 1.8 v 18 7.8 v (no noise detected) short time; typical 12 m s, valid for noise detected and v 18 3 1.2 v. when v 18 drops below 1.2 v, the integration time is forced back to 19 m s to prevent switching of the divider system to the wide window mode for noise only conditions. sync separator, phase detector and tv-station identi?cation (pins 5, 6, 7 and 18) sync separator the video input signal is connected to pin 5. the sync separator is designed such that the slicing level is independent of the amplitude of the sync pulse. the black level is measured and stored in the capacitor at pin 7. the slicing level is stored in the capacitor at pin 6. the slicing level value can be chosen by the value of the external resistor connected between pins 6 and 7. the value is given by the formula: where r s is the resistor connected between pins 6 and 7 and the top sync levels equals 100%. the recommended resistor value is 5.6 k w . black level detector a gating signal is used for the black level detector. this signal is composed of an internal horizontal reference pulse with a duty factor of 50% and the flyback pulse at pin 12. in this way the tv transmitter identification operates also for all dc conditions at input pin 5 (no video modulation, plain carrier only). during the vertical blanking interval the slicing detector is inhibited by a signal which starts with the anti-top-flutter pulse and ends with the reset of the vertical divider circuit. in this way shift of the slicing level due to the vertical sync signal is reduced and separation of the vertical sync pulse is improved. an internal noise inverter is activated when the video level at pin 5 decreases below 0.7 v. p r s 5.3 r s --------------------- - 100 r s value in k w () . =
january 1994 8 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C noise level detector the ic also embodies a built-in sync pulse noise level detection circuit. this circuit is directly connected to pin 5 and measures the noise level at the middle of the horizontal sync pulse. when a signal-to-noise level (s/n) of 19 db is detected a counter circuit is activated. s/n a video input signal is processed as "acceptable noise free" when 12 out of 15 sync pulses have a noise level below 19 db for successive field periods. the sync pulses are processed during a 15 line width gating period generated by the divider system. the measuring circuit has a built-in noise level hysteresis of approximately 3 db. the use of a filter of 1 k w and 150 pf in front of pin 5 reduces the noise content of the cvbs signal by approximately 6 db. when the "acceptable noise free" condition is found the phase detector of pin 8 is switched to not gated and normal time constant. when a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync pulse detection. at the same time the integration time of the vertical sync pulse separator is reduced providing v 18 > 1.2 v. phase detector ( see f ig .3) the phase detector circuit is connected to pin 8. this circuit consists of 3 separate phase detectors which are activated depending on the voltage of pin 18 and the state of the sync pulse noise detection circuit. for normal and fast time constants all three phase detectors are activated during the vertical blanking period, this with the exception of the anti-top-flutter pulse period, and the separated vertical sync pulse time. as a result, phase jumps in the video signal related to the video head, take over of video recorders are quickly restored within the vertical blanking period. at the end of the blanking period the phase detector time constant is increased by a factor of 1.4. in this way there is no requirement for external vtr time constant switching, and thus all station numbers are suitable for signals from vtr, video games or home computers. = 20 log video voltage (black-to-white signal) noise (rms) ----------------------------------------------------------------------------------------------- - for quick locking of a new tv station starting from a noise only signal condition (normal time constant) a special circuit is incorporated. a new tv station which is not locked to the horizontal oscillator will result in a voltage decrease below 0.1 v at pin 18. this will activate a field period counter which switches the phase detector to fast for 3 field periods during the vertical scan period. the horizontal oscillator will now lock to the new tv station and as a result, the voltage on pin 18 will increase to approximately 6.5 v. when pin 18 reaches a level of 1.8 v the mute output transistor of pin 13 is switched off and the divider is set to the large window. in general the mute signal is switched off within 5 ms (c 18 = 47 nf) after reception of a new tv signal. when the voltage on pin 18 reaches a level of 5 v, usually within 15 ms, the field counter is switched off and the time constant is switched from fast to normal during the vertical scan period. if the new tv station is weak, the sync noise detector is activated. this will result in a change over of pin 18 voltage from 6.5 v to approximately 10 v. when pin 18 exceeds the level of 7.8 v the phase detector is switched to slow time constant and gated sync pulse condition. the phase detector output current during the blanking period is now reduced from 2 ma to 1.35 ma. when desired, most conditions of the phase detector can also be set by external means in the following way: fast time constant, tv transmitter identification circuit not active, connect pin 18 to ground (pin 9) fast time constant, tv transmitter identification circuit active, connect a 220 k w resistor between pin 18 and ground; this condition can also be set by using a 3.6 v stabistor diode instead of a resistor slow time constant (with the exception of the vertical blanking period), connect pin 18 via a 10 k w resistor to +12 v (pin 10); in this condition the transmitter identification circuit is not active no switching to slow time constant required (transmitter identification circuit active), connect a 6.8 v zener diode between pin 18 and ground.
january 1994 9 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C fig.3 operation of the three phase detector circuits. mga792 mute (pin 13) gating 1 detector j voltage (pin 18) i 8 0.35 ma 1 detector j not gated i 8 1.0 ma 2 detector j not gated i 8 0.65 ma 3 detector j abcdefg 1 0 1 0 1 0 1 0 1 0 0.1 v 1.2 v 1.8 v 3.5 v 5 v 7.8 v explanation of areas a to g shown in fig.3 a switching over to new tv station activates 3 ?eld period counter b noise only condition c tv transmitter identification hysteresis range d fast time constant c-e fast time constant hysteresis range f normal time constant g sync pulse noise level detection circuit forces pin 18 to > 7.8 v while signal-to-noise level < 19 db; slow time constant and gated sync pulse operation. supply (pins 9, 10 and 16) the ic has been designed such that the horizontal oscillator and output stage operate a very low supply current into pin 16. the horizontal oscillator starts at a supply current of approximately 4 ma (v 16 approximately 6 v). the horizontal output stage is forced into the non-conducting stage until the supply current has reached a typical value of 5 ma. the circuit has been designed such that after starting the horizontal output function, a current drop of approximately 1 ma is allowed. the starting circuit has the ability to derive the main supply (pin 10) from the horizontal output stage. the horizontal output signal can also be used as oscillator signal for synchronized switched-mode power supplies.
january 1994 10 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C the maximum allowed starting current is 9.7 ma (t amb =25 c). the main supply should be connected to pin 10 and pin 9 should be used for ground. when the voltage on pin 10 increases from zero to its final value (typ. 12 v) a part of the supply current of the starting circuit is taken from pin 10 via internal diodes and the voltage on pin 16 will stabilize on a typical value of 9.3 v. in stabilized conditions (v 10 > 10 v) the minimum required supply current into pin 16 is approximately 2.5 ma. all other ic functions are switched on via the main supply voltage on pin 10. when this voltage reaches a value of approximately 7 v the horizontal phase detector is activated and the vertical ramp on pin 3 is started. the second phase detector circuit and burst pulse circuit are started when the voltage on pin 10 reaches the stabilized voltage value of pin 16 typical 9.3 v. to close the second phase detector loop a flyback pulse must be applied to pin 12. when no flyback pulse is detected the duty factor of the horizontal output stage is 50%. for remote switch-off pin 16 can be connected to ground (via a npn transistor with a collector series resistor of approximately 500 w ) which decreases pin 16 voltage to 5 v and switches off the horizontal output pulse. horizontal oscillator, horizontal output transistor and second phase detector the horizontal oscillator is connected to pin 15. the frequency is set by an external rc combination between pin 15 and ground (pin 9). the open collector horizontal output stage is connected to pin 11. an internal zener diode configuration limits the open voltage of pin 11 to approximately 14.5 v. the horizontal output transistor at pin 11 is blocked until the current into pin 16 reaches a value of approximately 5 ma. a higher current results in a horizontal output signal at pin 11, which starts with a duty factor of approximately 40% high. the duty factor is set by an internal current-source-loaded npn emitter follower stage connected to pin 14 during starting. when pin 16 changes over to voltage stabilization the npn emitter follower and current source load at pin 14 are switched off and the second phase detector is activated, provided a horizontal flyback pulse is present at pin 12. when no flyback pulse is detected at pin 12 the duty factor of the horizontal output stage is set to 50%. the phase detector circuit at pin 14 compensates for storage time in the horizontal deflection output state. the horizontal output pulse duration is 29 m s high for storage times between 1 m s and 17 m s (flyback pulse of 12 to 29 m s). a higher storage time increases the high time. horizontal picture shift is possible by forcing an external charge or discharge current into the capacitor at pin 14. mute output and 60 hz identi?cation (pin 13) the collector of an npn transistor is connected to pin 13. when the voltage on pin 18 drops below 1.2 v (no tv transmitter) the npn transistor is switched on. when the voltage on pin 18 increases to a level of approximately 1.8 v (new tv transmitter found) the npn transistor is switched off. this function is available when pin 13 is connected to pin 10 (+12 v) via an external pull-up resistor of 10 to 20 k w . when no tv transmitter is identified the voltage on pin 13 will be low ( < 0.5 v). when an m-system tv transmitter with a divider ratio < 576 (60 hz) is found an internal pnp transistor with its emitter connected to pin 13 will force the output voltage down to approximately 7.6 v. sandcastle output (pin 17) the sandcastle output pulse generated at pin 17 has three different voltage levels. the highest level (10.4 v) can be used for burst gating and black level clamping. the second level (4.5 v) is obtained from the horizontal flyback pulse at pin 12 and is used for horizontal blanking. the third level (2.5 v) is used for vertical blanking and is derived via the vertical divider system. for 60 hz the blanking pulse duration is 34 clock pulses started from the reset of the vertical divider system. for tv signals which have a divider ratio between 522 and 528 the vertical blanking pulse is started at the first equalizing pulse.
january 1994 11 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C limiting values in accordance with absolute maximum rating system (iec 134). thermal resistance characteristics v p = v 10 = 12 v; i 16 = 6.2 ma; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit i 16 start current v 10 = 0 v - 9.7 ma v p supply voltage - 13.2 v p tot total power dissipation - 1.2 w t stg storage temperature - 55 +150 c t amb operating ambient temperature - 25 +70 c symbol parameter thermal resistance r th j-a from junction to ambient in free air 50 k/w symbol parameter conditions min. typ. max. unit supply v p supply voltage (pin 10) 10 12 13.2 v i 16 supply current (pin 16) note 1 v 10 = 0 v 6.2 - 9.7 ma v 10 = 1 to 10 v; t amb 70 c 6.2 - 8.7 ma v 10 > 10 v 2.5 - 9.7 ma v 16 stabilized voltage (pin 16) 8.8 9.3 9.7 v i 10 current consumption (pin 10) - 70 85 ma video input (pin 5) v 5 top sync level 1.5 3.1 3.75 v v 5(p-p) sync pulse amplitude (peak-to-peak value) note 2 0.05 0.6 1 v sl slicing level note 3 35 50 65 % t d delay between video input and detector output see fig.5 0.2 0.3 0.55 m s s/n signal-to-noise ratio with sync pulse noise level detector circuit active cvbs = 1 v without ?lter at pin 5; note 4 - 19 - db sync pulse hys noise level detector circuit hysteresis - 3 - db noise gate (pin 5) v 5 switching level - 0.7 1 v
january 1994 12 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C first control loop (pin 8) horizontal oscillator to synchronization signal d f holding range 700 800 - hz d f catching range 700 800 1100 hz a cs control sensitivity video with respect to burst key and ?yback pulse: slow time constant note 5 - 2 - khz/ m s normal time constant note 6 - 5 - khz/ m s fast time constant note 6 - 3 - khz/ m s j 10 phase modulation due to hum on the supply line (peak-to-peak value) note 7 - 0.2 -m s/v j 16 phase modulation due to hum on the input current (peak-to-peak value) note 8 - 0.08 -m s/v second control loop (pin 14) horizontal ?yback to horizontal oscillator d t d / d t o control sensitivity t d = 10 m s 200 300 600 m s/ m s t d control range 1 - 45 m s t d control range for constant duty factor horizontal output 129 - t fb -m s control edge of horizontal output signal (pin 11) - positive - phase adjustment (pin 14) via second control loop a cs control sensitivity t d = 10 m s - 25 -m a/ m s i 14 maximum allowed control current -- 60 m a horizontal oscillator (pin 15) c osc = 2.7 nf; r osc = 34.2 k w f h frequency (no sync) - 15 625 - hz d f h spread (?xed external components, no sync) -- 4% d f h frequency deviation between starting point output signal and stabilized condition - +5 +8 % tc temperature coef?cient -- 1.10 -4 - k horizontal output (pin 11) open collector v 11h high level output voltage -- 13.2 v v 11 start voltage protection (internal zener diode) 13 - 15.8 v i 16l low level input current protection output enabled - 5.0 6.2 ma v 11l low level output voltage start condition i 11 = 10 ma - 0.1 0.5 v d duty factor output current during starting i 16 = 6.2 ma 50 60 70 % v 11l low level output voltage normal condition i 11 = 25 ma - 0.3 0.5 v d duty factor output current without ?yback pulse pin 12 45 50 55 % symbol parameter conditions min. typ. max. unit
january 1994 13 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C t oh duration of output pulse high storage time horizontal de?ection stage = 10 m s 27 29 31 m s tc temperature coef?cient -- 4.10 -2 - k d h w /h d in?uence of delay time on pulse width of horizontal output signal - 0.16 -m s/ m s controlled edge - positive - sandcastle output signal (pin 17) v 17 output voltage during: burst key 9.8 10.4 - v horizontal blanking i load = 1 ma 4.1 4.5 4.9 v vertical blanking i load = 0.3 ma 2.1 2.5 2.9 v v 17 zero level output voltage i sink = 0.5 ma - 0.7 - v t p burst key pulse width 60 hz 3.4 3.65 4 m s v 12 horizontal blanking level - 1 - v vertical blanking note 9 t d1 phase position burst key time between middle sync pulse at pin 5 and start burst key pulse at pin 17 2.3 2.7 3.1 m s t d2 phase position burst key time between start sync pulse at pin 5 and end of burst key pulse at pin 17 60 hz -- 9.1 m s coincidence detector, video transmitter identi?cation circuit and time constant switching levels (see fig.1) i 18 detector output current - 0.25 - ma v 18 voltage level for in sync condition j 1 normal 5.8 6.4 7 v v 18 voltage level for noisy sync pulse j 1 slow and gated 9 10.1 - v v 18 voltage level for noise only note 10 - 0.3 - v v 18 switching level: normal to fast < 3.2 3.5 3.8 v mute output active and fast to normal < 1.0 1.2 1.4 v ?eld period counter 3 periods fast < 0.08 0.12 0.16 v normal to fast mute output inactive locking > 1.5 1.75 2 v fast to normal locking > 4.7 5 5.3 v normal to slow gated sync pulse > 7.4 7.8 8.2 v video transmitter identi?cation output (pin 13) v 13 output voltage active no sync; i 13 = 2 ma - 0.15 0.32 v i 13 sink current active no sync; v 13 = 1 v -- 5ma i 13 output current inactive sync 60 hz -- 1 m a 60 hz identi?cation (pin 13) r 13 positive supply 15 k w v 13 pnp emitter follower voltage note 11 7.2 7.65 8.1 v symbol parameter conditions min. typ. max. unit
january 1994 14 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C flyback input pulse (pin 12) v 12 switching voltage level - 0.9 - v i 12 input current 0.2 - 3ma v 12(p-p) input pulse (peak-to-peak value) -- 12 v r 12 input resistance - 3.5 - k w t d phase position without shift; time between the middle of the sync pulse at pin 5 and the middle of the horizontal blanking pulse at pin 17 2.1 2.5 2.9 m s vertical ramp generator (pin 3) t c charge current pulse width - 26t clk - i 3 charge current - 3 - ma v 3 top level ramp signal voltage divider in 60 hz mode note 12 4.55 4.85 5.25 v v 3(p-p) ramp amplitude (peak-to-peak value); r 4 = 330 k w ; f v = 60 hz c 3 = 150 nf; note 12 - 2.5 - v current source (pin 4) v 4 output voltage i 4 = 20 m a 7 7.5 7.9 v i 4 allowed current range t amb = 25 to 70 c10 - 75 m a tc temperature coef?cient output voltage i 4 = 40 m a - 50 - 10 -6 /k current source (pin 3) i 3/4 current ratio pin 3/pin 4 i 4 = 35 m a; v 3 = 2 v - 1.05 - tc temperature coef?cient i 3 i 4 = 40 m a; r 4 ?xed - 100 - 10 -6 /k comparator (pin 2) v 2 input voltage dc level r 4 = 330 k w ; c 3 = 150 nf 0.98 1.075 1.17 v v 2(p-p) input voltage ac level (peak-to-peak value) r 4 = 330 k w ; c 3 = 150 nf - 0.8 - v i 2 input current v 2 = 0 v -- 1 m a vertical output stage (pin 1) npn emitter follower v 1 maximum output voltage i 1 = +1.5 ma; note 12 5 5.5 6.3 v r s sync separator resistor - 170 -w i sink continuous sink current - 0.25 - ma vertical guard circuit (pin 2) v 2h active switching level high v 17 = 2.5 v; note 12 > 1.7 1.85 2.0 v v 2l active switching level low v 17 = 2.5 v; note 12 < 0.25 0.35 0.45 v symbol parameter conditions min. typ. max. unit
january 1994 15 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C notes to the characteristics 1. value inclusive r l pin 11 to pin 16 = 6.8 k w . 2. up to 1 v peak-to-peak the slicing level is constant, at amplitudes exceeding 1 v peak-to-peak the slicing level will increase. 3. the slicing level is fixed by the formula: where r s is the resistor between pins 6 and in k w ; top sync = 100%. 4. s/n a low-pass filter of 1 k w and 150 pf decreases the noise content of the cvbs signal by 6 db. 5. undercompensated. 6. overcompensated. 7. measured between pin 5 and sandcastle output pin 17. 8. measured with 3.3 m f feedback capacitor between pin 16 and 6.8 m f capacitor in pll filter pin 8. 9. maximum divider ratio (60 hz): start vertical blanking: - search (large) window mode (60 hz) - reset divider = start vertical sync pulse plus 1 clock pulse - small/standard window mode (60 hz) - clock pulse 517. stop vertical blanking: - all window modes (60 hz) - clock pulse 34. 10. depends on dc level of pin 5, value given is valid for v 5 ? 5v. 11. valid for 12. value related to internal zener diode reference voltage. spread includes complete spread of reference voltage. internal vertical sync pulse separator t d1 delay between video signal at pin 5 and internally separated vertical sync pulse; normal signal condition 12 19 25 m s t d2 delay between video signal at pin 5 and internally separated vertical sync pulse; noisy signal condition v 18 3 1.2 v -- - 17 m s symbol parameter conditions min. typ. max. unit p r s 5.3 r s -------------------- - 100%. = = 20 log video voltage (black-to-white signal) noise (rms) ----------------------------------------------------------------------------------------------- - n 2f h f v -------------- 576 (2 clock pulses per video line). == 2f h f v -------------- 576. <
january 1994 16 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C fig.4 counter system. 10 26 34 130 160 488 525 517 528 576 0 start vertical sawtooth charge pulse blocking pulse phase detector 1 vertical blanking search mode end of blocking pulse (60 hz) end of vertical sawtooth charge pulse end of vertical blanking (60 hz) noise detector window start blocking pulse phase detector 1 (60 hz) vertical blanking (60 hz) normal and narrow window normal reset reset divider when mute is active; no vertical sync found 60 hz identification search window mga793 one video line equals two counter pulses. reset counter 32 m s after start of vertical sync pulse at pin 5. reset counter = counter state 0.
january 1994 17 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C fig.5 timing diagram. two counter pulses equals one video line. mga794 10.4 v 4.5 v 1/2 t fb storage time horizontal deflection stage switching level video input separated horizontal sync pulse horizontal oscillator sawtooth internal gating pulse 0v 2.5 v reference j detector 1 output i 8 j detector 1 j reference level 1 2 j reference level 0.3 s m 4.7 s m 5-9 signal v horizontal flyback pulse 2.5 s m 7.5 s m 3.75 s m 3.75 s m coincidence detector 18 output i reference j detector 2 external horizontal flyback pulse v 12-9 output i 14 j detector 2 29 s m horizontal output signal v 11-9 sandcastle output signal v 17-9 0.2 s m t p 12 s m 6 s m 0.7 v divider in search window mode 60 hz: 34 clock pulses other divider modes 60 hz: 42 clock pulses 1/2 t fb t fb
january 1994 18 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C mga796 w 560 w 880 c 8.4 w k w 560 w 880 c 4.7 w k w 560 w 880 c 2.4 w k 2.4 w k 9.5 w k 4 w k d 18 w k w 36 k v 2.8 v ref detector j 1 c a b 9 w k w 360 5.6 w k a 6.2 w k a 4.3 w k sync separator 2 v reference 0 v w 1 k 150 pf w 2 k w 10 k a 11 w k 10.5 w k 1 w k 6 w k b 2 w k 3.5 w k noise detector 5 video input 7.7 w k w 1.5 k 1.3 w k w 1.5 k w 200 i v stab vertical sawtooth generator 2.15 w k w 2 k i k w 160 w 150 2 w k m a 250 m a 250 w 5.1 k w 1 k w 12 k 1.2 w k 12 w k 60 hz identification 6 w k 11 w k 2.7 w k w 1.8 k 1.4 ma w 160 0.8 ma 1.4 ma w 1 k j 2 detector stabilizer 5.6 w k 11 w k g h pin 16 pin 10 g start up w 3.9 k w 2.2 k w 2.2 k j 2 i h g ii i pin 16 start up e f pin 10 e f d w 220 stabilizer 6.2 w k detector j 2 horizontal oscillator horizontal flyback horizontal output vertical comparator v stabilizer vertical driver coincidence detector transmitter identification sandcastle supply 12 v 6.8 w k pin 16 3.0 ma 0.2 ma 100 nf w 33 k w 4.7 k 2.7 nf w 1.2 k 68 nf m f 6.8 w 22 m f 22 m f 2.2 5.6 w k m f 4.7 3.6 w k 43 w k 150 nf 150 w k 220 w k 4.3 w k 4.3 w k 100 nf 15 w k 12 v TDA2579C 4 3 2 1 18 13 17 9 16 10 11 12 14 15 8 7 6 k fig.6 internal circuitry
january 1994 19 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C fig.7 TDA2579C and tda3654 combination 110 flat square picture tube. (1) dependent on printed-circuit board layout. mga795 9 100 nf 12 10 16 15 85 13 14 76 11 4.7 nf sandcastle horizontal drive horizontal flyback 150 nf 4321 17 22 m f 68 nf 6.8 m f w 1.2 k video input 22 m f w 22 w 5.6 k 100 nf 12 v 26 v 18 2.2 m f 150 pf 220 w k 150 w k w k 1 w 0.5 w 3.6 k 4.7 m f TDA2579C 47 w k w 6.8 k 100 m f w 12 k w 39 k 0.2 to 3.0 ma horizontal shift 2.7 nf 100 w k 33 w k 4.7 w k f adj. o start voltage 6.2 ma to 9.7 ma transmission identification 60 hz identification 10 nf w 1 k w 1 k w 43 k 1000 m f deflection coil w 270 w 4.3 k w 4.3 k 470 pf (1) 220 m f w 560 w 4.7 100 m f bax12 vertical deflection circuit tda3654 98 5 76 4321 1 nf 10 nf (1)
january 1994 20 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C package outline fig.8 18-lead dual in-line; plastic (sot102). dimensions in mm. 8.25 7.80 0.32 max 7.62 9.5 8.3 msa259 18 1 10 9 1.4 max 6.48 6.14 22.00 21.35 3.7 max 4.7 max 0.51 min 3.9 3.4 seating plane 0.254 m 0.53 max 2.54 (8x) 0.85 max soldering plastic dual in-line packages b y dip or wave the maximum permissible temperature of the solder is 260 c; this temperature must not be in contact with the joint for more than 5 s. the total contact time of successive solder waves must not exceed 5 s. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply the soldering iron below the seating plane (or not more than 2 mm above it). if its temperature is below 300 c, it must not be in contact for more than 10 s; if between 300 and 400 c, for not more than 5 s.
january 1994 21 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
january 1994 22 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C notes
january 1994 23 philips semiconductors preliminary speci?cation synchronization circuit with synchronized vertical divider system for 60 hz TDA2579C notes
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(0212)269 3094 united kingdom: philips semiconductors limited, p.o. box 65, philips house, torrington place, london, wc1e 7hd, tel. (071)436 41 44, fax. (071)323 03 42 united states: integrated circuits: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 2001 west blue heron blvd., p.o. box 10330, riviera beach, florida 33404, tel. (800)447-3762 and (407)881-3200, fax. (407)881-3300 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building baf-1, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd27 ? philips electronics n.v. 1993 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 9397 725 20011

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